Synopsys Acquires Co-Design Automation to Accelerate Delivery of Next-Generation HDL With SUPERLOG Technology
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--August 28, 2002--
Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex
integrated circuit (IC) design, today announced it has signed a
definitive agreement to acquire all outstanding shares of Co-Design
Automation, a privately held verification company focused on improving
the designer's ability to efficiently create and verify system-on-chip
(SoC) designs. The combination of Co-Design Automation technology with
Synopsys' industry-proven VCS(TM) Verilog simulator will enable
delivery of next-generation hardware description language (HDL)
solutions. Consideration for the merger consists of cash, notes and
assumed options with an aggregate value of approximately $36 million.
Co-Design Automation is the developer of SUPERLOG®, a
state-of-the-art language technology that extends the standard Verilog
HDL with powerful high-level programming techniques and advanced
verification and behavioral modeling capabilities that allow users to
easily evolve their existing design and verification methodologies.
"Co-Design Automation assembled many of the world's leading
Verilog language experts to deliver SUPERLOG technology," stated Aart
de Geus, chairman and CEO of Synopsys. "The addition of Co-Design
Automation to Synopsys comes at the very moment that SystemVerilog,
the next-generation Verilog language, is coming about. Having
technology pioneers such as Phil Moorby, Peter Flake and Simon
Davidmann join our team of verification experts significantly
accelerates our Smart Verification strategy. The combination of
Synopsys' recent VCS 7.0 release, SUPERLOG technology and the
Accellera SystemVerilog umbrella will drive the state-of-the-art of
RTL design and verification forward in very short order and decisively
impact design productivity."
"Joining forces with the Synopsys team is a strong step toward
furthering advanced Verilog methodologies which will address the
immense verification challenge our customers are facing," said Simon
Davidmann, chief executive officer of Co-Design Automation. "Synopsys'
leadership in verification, coupled with Co-Design Automation's
strength in design language technology, will accelerate language
evolution and thus enable new levels of design and verification
productivity across the industry."
"We believe that both Intel and the industry will be better served
by a higher abstraction language, and we have worked closely with
Synopsys and Co-Design Automation to evolve such a verification
standard," said Sunil Shenoy, director of design engineering at Intel.
"Integrating the two companies' technologies will accelerate the
adoption of the high-level Verilog standard in the design engineering
community."
"Our partners need to efficiently verify ARM® cores within their
overall SoC designs. We need to deliver robust verification
environments to those licensees, including comprehensive design and
verification views. SUPERLOG and Smart Verification provide
technologies to achieve efficient verification critical for core-based
design," said Simon Segars, vice president of engineering at ARM.
"Combining these technologies is great news for us and our partners
who incorporate our cores into their designs."
About Co-Design Automation
Co-Design Automation is a design and verification company focused
on improving the large scale design methodologies. The company has
developed a powerful new design language, based on Verilog and C,
known as SUPERLOG. Co-Design Automation was founded in 1997 and has
its corporate headquarters in Los Altos, Calif.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View,
California, creates leading electronic design automation (EDA) tools
for the global electronics market. The company delivers advanced
design technologies and solutions to developers of complex integrated
circuits, electronic systems and systems on a chip. Synopsys also
provides consulting and support services to simplify the overall IC
design process and accelerate time to market for its customers. Visit
Synopsys at http://www.synopsys.com.
Note to Editors: Synopsys is a registered trademark and VCS is a
trademark of Synopsys, Inc. SUPERLOG is a registered trademark of
Co-Design Automation, Inc. All other trademarks or registered
trademarks mentioned in this release are the intellectual property of
their respective owners.
Contact:
Synopsys, Inc., Mountain View
Yvette Huygen, 650/584-4547
yvetteh@synopsys.com
Jessica Kourakos, 650/584-4289 (Investors)
jessicak@synopsys.com
or
Edelman Worldwide PR
Darren Ballegeer, 650/429-2735
darren.ballegeer@edelman.com
